abridged data sheet MAXQ1103 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated? website at www.maximintegrated.com. evaluation kit available deepcover secure microcontroller with rapid zeroization technology and cryptography 19-5091; rev 5; 1/13 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through vari ous sales channels. for information about device errata, contact the factory. general description deepcover embedded security solutions cloak sensi-tive data under multiple layers of advanced physical security to provide the most secure key storage possible. the deepcover secure microcontroller (MAXQ1103) is a low-power, 32-bit risc device that combines high- performance, single-cycle processing, sophisticated tamper-detection technology, and cryptographic hard- ware. advanced security features are designed to meet the stringent requirements of regulations such as itsec e3 high, fips 140-2 level 3, and the common criteria certifications. the MAXQ1103 is targeted at electronic commerce, banking, and data security systems that require the highest levels of secure access control, secure data storage, digital signature, or certificate authentication. a secure memory protection unit pro- tects critical internal and external memory against tam- pering with triple-des (3des) encryption. activation of a tamper sensor causes a rapid zeroization of critical data. an internal physical shield layer increases the complexity and cost of a physical attack against the die . a 32-bit maxq30 core powers the cryptographicallysecure MAXQ1103. applications are supported with 512kb of high-performance internal flash memory for code/data storage and 32kb sram. up to 8mb of additional external program and data memory is sup- ported through a dedicated word-wide memory bus with programmable wait states. additional peripherals such as serial i/o, 16-bit timers, hardware math accel- erator, iso 7816 uart, and a usb controller increase system utility while reducing component count. system security is enhanced by the addition of high- speed cryptographic hardware accelerators for ecdsa, dsa, rsa, secure hash algorithm, and triple- key 3des. the embedded hash engine supports multi- ple hash functions recommended by the national institute of standards and technology (nist). the true hardware random-number generator (rng) supports fips 186-2 with an available software library. applications features ? high-performance 32-bit maxq30 risc core ? dc to 25mhz operation, approaching 1mips per mhz ? dual 1.8v core/3.3v i/o enables low power/flexible interfacing ? 5v tolerant i/o ? up to 32 general-purpose i/o pins ? 34 instructions, most single cycle ? three independent data pointers accelerate datamovement with automatic increment/decrement ? virtually unlimited software stack ? 16-bit instruction word, 32-bit internal data bus ? 16 x 32-bit accumulators ? security features 3des-encrypted external memory bus prevents eavesdropping tamper sensors rapidly ?eroize?internal keys and user data when: out-of-range temperature/voltage detecteduser-defined self-destruct inputs (sdix) activated internal cryptographic hardware includes: des engine supporting single des and 2/3-key 3des operations public-key cryptographic accelerator for ecdsa (160-, 192-, and 256-key strength) public-key cryptographic accelerator for dsa and rsa (1024- and 2048-key strength) hardware hash engine supports sha-1, sha-224, and sha-256 unresettable true-time clock self-imposes expiration dates and date/timestamping ? memory features secure memory protection unit and 4kb instruction cache 512kb of internal flash program memory3kb internal program memory sram 32kb internal data sram, including 1kb battery- backed nv sram linear address space directly accesses up to 8mb of external program/data memory ? peripheral features usb device controller with four endpoint buffersiso 7816 uart with fifo with two physically separate communication buses ? power management features ? in-system programming through debug port orserial port ? ultra-low battery leakage to support nv ramand security sensors (150na) ordering information deepcover is a trademark and maxq is a registered trademark of maxim integrated products, inc. emv is a registered trademark of emvco, llc. see the detailed features section for complete list of features. part temp range pin- package tamper responsie MAXQ1103-ens+ -40 c o +85 c 144 tqfp yes + denotes a lead(pb)-free/rohs-compliant package. pin configuration and typical application circuit appear at end of data sheet. electronic commercepci terminals pin pads atm keyboards emv banking secure access controlsecure data storage pay-per-play certificate authentication electronic signature generator downloaded from: http:///
abridged data sheet deepcover secure microcontroller with rapid zeroization technology and cryptography MAXQ1103 maxim integrated 15 note to readers: this document is an abridged version of the full data sheet. to request the full data sheet, go to www.maximintegrated.com/MAXQ1103 and click on request full data sheet . functional diagram 2048-bit modulo arithmetic accelerator maxq30 pipelined risc core internal data memory internal program memory mmu data memory encryptor/ decryptor 16k x 16 sram high/low temperature sensors external code integrity checker des/3des program memory decryptor instruction cache 2k x 16 512 x 16 sram 16k x 16 rom 256k x 16 flash 1.5k x 16 sram des keys external program and data memory interface random-number generator (rng) crc-16/32 generator real-time clockclock generation internal 20mhz osc watchdog pll (4x/2x) battery backed 32kin 32kout gnd2 reset and destruct reset reset prog sdi[1:7] hfxin hfxout sdbe power- supply monitoring des/3des user engine internal 55mhz osc multiply- accumulate unit sha b0 b1 b2 b3 pcs1 pcs1n pcs2 pcs2n dcs1 dcs1n dcs2 dcs2n pes1 pes2 ed[31:0] ad[19:0] usb v ddio (+3.3v) v dd (+1.8v) v bat (+3v) gnd vrst pf v ddo r/w usart 0 timer 2 jtag port 3 timer 3 port 2 edge interrupts timer 1 usart 1 port 1 timer 0 iso 7816 uart and fifo port 0 MAXQ1103 downloaded from: http:///
|
